PROGRAM
4th Workshop on
Highly Parallel Processing on a Chip (HPPC 2010)
August 31, 2010, Ischia - Naples, Italy
in conjunction with
August 31- September 3, 2010, Ischia - Naples, Italy.
TUESDAY AUGUST 31, 2010
SESSION 1 - Models and memory organizations
09:30-09:35 Opening remarks - Jesper Larsson Träff and Martti Forsell, University of Vienna, VTT
09:35-10:35 Keynote - The Massively Parallel Computing Model GCA - Rolf Hoffmann, Technical University of Darmstadt
10:35-11:00 Low-Overhead Organizations for the Directory in Future Many-Core CMPs - Alberto Ros and Manuel E. Acacio, Technical University of Valencia, University
of Murcia
11:00-11:30 -- Break --
SESSION 2 - Programming multicores
11:30-11:55 A Work Stealing Algorithm for Parallel Loops on Shared Cache Multicores - Marc Tchiboukdjian, Vincent Danjean, Thierry Gautier, Fabien Le Mentec and Bruno
Raffin, CNRS - CEA/DAM, DIF, Grenoble University, INRIA
11:55-12:20 Resource-agnostic programming for many-core microgrids - Thomas Bernard, Clemens Grelck, Michael Hicks, Christopher Jesshope and Raphael
Poss, University of Amsterdam
12:20-12:45 Programming Heterogeneous Multicore Systems using Threading Building Blocks - George Russell, Paul Keir, Alastair Donaldson, Uwe Dolinsky, Andrew Richards and
Colin Riley, Codeplay Software, University of Glasgow, Oxford University
12:45-15:30 -- Lunch --
SESSION 3 - Applications and optimizations
15:30-15:55 Fine-grained parallelization of a Vlasov-Poisson application on GPU - Guillaume Latu, CEA, IRFM
15:55-16:20 Highly Parallel Implementation of Harris Corner Detector on CSX SIMD
Architecture - Fouzhan Hosseini, Amir Fijany and Jean-Guy Fontaine, Italian Institute of
Technology
16:20-16:45 Static Speculation as Post-Link Optimization for the Grid Alu Processor - Ralf Jahr, Basher Shehan, Sascha Uhrig and Theo Ungerer, University of Augsburg
16:45-17:30 -- Break --
SESSION 4 - Networks and clouds
17:30-17:55 A Multi-Level Routing Scheme and Router Architecture to support Hierarchical
Routing in Large Network on Chip Platforms - Rickard Holsmark, Shashi Kumar and Maurizio Palesi, Jönköping University, University of Catainia
17:55-18:55 Keynote - Intel Lab’s “Single-chip Cloud Computer”, an IA Tera-scale Research Processor - Jim Held, Tera-Scale Computing Research, Intel
18:55-19:00 Closing remarks - Jesper Larsson Träff and Martti Forsell, University of Vienna, VTT
Submission:
June 14, 2010
Notification:
July 26, 2010
Workshop:
August 31, 2010
Final LNCS paper:
September, 2010
Registration:
via Euro-Par
Contact:
chair@hppc-
workshop.org
Sponsors:
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