PROGRAM
5th Workshop on
Highly Parallel Processing on a Chip (HPPC 2011)
August 30, 2011, Bordeaux, France
in conjunction with
August 29 - September 2, 2011, Bordeaux, France.
TUESDAY AUGUST 30, 2011
SESSION 1 - High throughput computing CMPs
09:30-09:35 Opening remarks - Jesper Larsson Träff and Martti Forsell, University of Vienna, VTT
09:35-10:35 Keynote - Extreme Thread-Level-Parallelism on Sparc Processors - Rick Hetherington, Microelectronics, Oracle Corp, USA
10:35-11:00 Thermal Management of a Many-Core Processor under Fine-Grained Parallelism - Fuat Keceli, Tali Moreshet and Uzi Vishkin, University of Maryland, Swarthmore
College
11:00-11:30 -- Break --
SESSION 2 - Programming and optimization of CMPs
11:30-11:55 Mainstream Parallel Array Programming on Cell - Paul Keir, Paul Cockshott and Andrew Richards, University of Glasgow, Codeplay
Software Ltd
11:55-12:20 Generating GPU Code from a High-level Representation for Image Processing
Kernels - Richard Membarth, Anton Lokhmotov and Jürgen Teich, University of Erlangen-Nuremberg, ARM
12:20-12:45 A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore
Processors - Thomas Canhao Xu, Pasi Liljeberg and Hannu Tenhunen, Turku Center for Computer
Science, University of Turku
12:45-12:50 Closing remarks - Jesper Larsson Träff and Martti Forsell, University of Vienna, VTT
12:50-14:30 -- Lunch --
14:30-15:00 Informal business meeting on the Highly Parallel Processing on a Chip Workshop
Series - Jesper Larsson Träff and Martti Forsell, University of Vienna, VTT
Submission:
June 10, 2011
Notification:
July 25, 2011
Workshop:
August 30, 2011
Final LNCS paper:
September, 2011
Registration:
via Euro-Par
Contact:
chair@hppc-
workshop.org
Sponsors:
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