INVITED TALKS
4th Workshop on
Highly Parallel Processing on a Chip (HPPC 2010)
August 31, 2010, Ischia - Naples, Italy
in conjunction with
August 31- September 3, 2010, Ischia - Naples, Italy.
KEYNOTE 1
The Massively Parallel Computing Model GCA
Rolf Hoffmann, Professor, Technical University of Darmstadt, Germany
Abstract: The Global Cellular Automata Model (GCA) is an extension of the Cellular
Automata Model (CA). Whereas in the CA model each cell is connected via fixed
links to its local neighbors, in the GCA model each cell is connected via data
dependant dynamic links to any (global) cells of the whole array. The GCA cell
state does not only contain data information but also link information. The
cell state is synchronously updated according to a local rule, modifying the
data and the link information. Similar to the CA model, only the own cell state
is modified. Thereby write conflicts cannot occur. The GCA model is related to
the CROW (concurrent read owners write) model and it can be used to describe a
large range of applications. GCA algorithms can be described in the language
GCA-L which can be compiled into different target platforms: a generated data
parallel multi-pipeline architecture, a NIOS II multi-softcore architecture and
a NVIDIA GPU.
Bio: Rolf Hoffmann is Professor and leader of the Computer Architecture Group in the
Computer Science Department of the Technical Unversity of Darmstadt Germany
since 1978. He graduated 1970 at TU Berlin (Dipl.-Ing. Electrical Engineering),
and received there 1974 the Ph.D. in Computer Science. He published a book on
Microprogramming and Computer Design and many papers on special computer
architectures and their FPGA implementations. Since 1994 several accelerators
for Cellular Automata (CEPRA series) were implemented in his group. He is
mainly working on novel massively parallel computing models; in particular he
proposed the Global Cellular Automata model.
KEYNOTE 2
Intel Lab’s “Single-chip Cloud Computer”, an IA Tera-scale Research Processor
Jim Held, Intel Fellow, Director Tera-Scale Computing Research, Intel, USA
Abstract: As part of our Tera-scale Computing Research Program, Intel Labs has created a
second generation experimental “Single-chip Cloud Computer,” (SCC). It contains the most Intel Architecture cores ever integrated on a
silicon CPU chip – 48 cores. It incorporates technologies intended to scale multi-core processors
to 100 cores and beyond, such as an on-chip network, advanced power management
technologies and support for “message-passing.”
Architecturally, SCC is a microcosm of a cloud datacenter. Each core can run a
separate OS and software stack and act like an individual compute node that
communicates with other compute nodes over the on-die packet-based network
fabric, thus supporting the "scale-out" message passing programming models that
have been proven to scale to 1000s of processors in cloud datacenters.
The SCC serves as an experimental platform for a wide range of software research
and is currently being used by a worldwide community of academic and industry
co-travelers. This talk will describe the architecture of the SCC platform and
discuss its role in the broader context of our Tera-scale research.
Bio: Jim is an Intel Fellow who leads a virtual team of architects conducting
Tera-Scale Computing Research in Intel Labs. Since joining Intel in 1990, he
has led research and development in a variety of Intel's labs concerned with
media and interconnect technology, systems software, multi-core processor
architecture and virtualization. He earned a Ph.D. (1988) in Computer and
Information Science at the University of Minnesota.
Submission:
June 14, 2010
Notification:
July 26, 2010
Workshop:
August 31, 2010
Final LNCS paper:
September, 2010
Registration:
via Euro-Par
Contact:
chair@hppc-
workshop.org
Sponsors:
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