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CALL FOR PAPERS |
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Context |
| - The
improvement of the processor performance by increasing the clock rate
has reached its technological limits. Increasing the number of
processor cores rather than clock rate can give better performance and
reduce problems like energy consumption, heat dissipation and design
complexity. We are witnessing the emergence of multi-core processors in
all markets from laptops and game consoles to servers and
supercomputers. |
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Topics
of Interest |
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topics of the workshop include but are not limited to: |
- multi-core architectures
- interconnection networks
- multi-core embedded systems
- programming languages and models
- algorithms for multi-core computing systems
- applications for multi-core systems
- performance modeling and evaluation of multi-core
systems
- design space exploration
- resource usage optimization
- tool-support for multi-core systems
- compilers, runtime and operating systems
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Submission Guidelines |
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papers should be prepared using the
IEEE CS format,
and no longer than 6 pages. Submitted papers will be carefully
evaluated based on originality, significance to workshop topics,
technical soundness, and presentation quality. |
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Submission of the paper implies that should the paper be accepted, at
least one of the authors will register and present the paper at the
workshop. Proceedings of the workshop will be published by IEEE
Computer Society Press. The best papers presented at the workshop will
be selected for publication in an
international journal. |
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papers should be
submitted electronically via
CISIS'08 website. |
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Important Dates |
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Submission: CLOSED |
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Notification: December 10, 2007 |
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Registration: December 20, 2007 |
| - Final
version of the paper: January 2, 2008 |
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Workshop: March 7, 2008 |
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Keynote
Address |
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TITLE: Petascale Computing for Large-Scale Graph Problems
(Presentation slides as PDF; Photos:
1, 2)
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SPEAKER: Prof. David A. Bader
Head of the Sony-Toshiba-IBM center of competence for the Cell BE processor.
Georgia Institute of Technology, USA
<http://www.cc.gatech.edu/~bader/> |
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Workshop Co-chairs |
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Leonard Barolli, Fukuoka Institute of Technology,
Japan |
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- Sabri
Pllana, University of Vienna, Austria |
| - Fatos
Xhafa, Polytechnic University of Catalonia, Spain |
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Program
Committee |
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David A. Bader, Georgia Institute of Technology, USA |
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Leonard Barolli, Fukuoka
Institute of Technology, Japan |
| - Siegfried Benkner, University of
Vienna, Austria |
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- Luca Benini,
University of Bologna, Italy |
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- François Bodin,
IRISA, University of Rennes, France |
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Rajkumar Buyya, University of Melbourne, Australia |
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Michel Cosnard, INRIA, France |
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- Nathalie Drach,
University of Paris VI - Pierre & Marie Curie, France |
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Michael Gschwind, IBM T.J. Watson Research Center, USA |
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Eleni Karatza, Aristotle University of Thessaloniki, Greece |
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Michael McCool, University of Waterloo, and RapidMind Inc., Canada |
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Pierre Michaud, IRISA/INRIA, France |
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- Bernd Mohr,
Research Centre Jülich, Germany |
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Lasse Natvig, Norwegian University of Science and Technology, Norway |
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- Mohamed
Ould-Khaoua, Sultan Qaboos University, Oman, and University of
Glasgow, UK |
| - Sabri
Pllana, University of
Vienna, Austria |
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- Vivek Sarkar,
Rice University, USA |
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Jie Tao, University of Karlsruhe, Germany |
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Jesper Larsson Träff, C&C Research labs, NEC Europe
Ltd, Germany |
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Manolis Vavalis, CERETETH, Greece |
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Brian Vinter, University of Copenhagen, Denmark |
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- Roland
Wismüller, University of Siegen, Germany |
| - Fatos
Xhafa, Polytechnic
University of Catalonia, Spain |
| - Hans
Zima, University of Vienna, Austria,
and JPL/Caltech, USA |
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Contact Person |
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- Sabri Pllana |
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University of
Vienna, Austria |
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T. +43 1 4277
39411 |
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F. +43 1 4277
9394 |
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E. pllana [at] par.univie.ac.at |
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<http://www.par.univie.ac.at/~pllana/> |
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Registration |
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| - The
workshop registration will be performed via CISIS'08 website. |
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