Workshop on Highly Parallel Processing on a Chip (HPPC)

Workshop on

Highly Parallel Processing on a Chip (HPPC)

August 28, 2007, IRISA, Rennes, France

in conjunction with

the 13th International European Conference on Parallel and Distributed Computing (Euro-Par07)

August 28-31, 2007, IRISA, Rennes, France.

AIMS AND SCOPE

With a number of both general and special purpose multi-core processors already on the market, it is foreseeable that new designs with a substantial number of processing cores will emerge to meet demands for extremely high performance, dependability, and controllable power consumption in mobile and embedded devices, and in response to the convergence of communication-, media- and compute devices. These developments raise new, architectural and methodological challenges, like:

° Design of multi-core architectures that support powerful, high-level programming models, and enables the full performance to be allocated to arbitrary and dynamically changing workloads ranging from a single computational problem to multiple dependent or independent tasks.

° Design of architectures capable of dealing with/hiding the latency of the memory system, supporting simultaneous exploitation of multiple levels of parallelism, and providing high intercommunication bandwidth.

° Design of power efficient architectures with dynamic control of power consumption.

° Design of architecture and software solutions to deal with limited off-chip memory and communication bandwidth.

° Development of (parallel) programming paradigms, languages, libraries, and support tools for efficient and manageable exploitation of highly parallel multi-core architectures.

The workshop on Highly Parallel Processing on a Chip is dedicated to all aspects of existing and emerging/envisaged multi-core processors with a significant amount of parallelism. Particular emphasis will be on the interaction between hardware (homogeneous, heterogeneous), architecture (processors, on-chip networks, cache and memory system), programming model and languages, and algorithms as well as applications in need of or benefitting from significant amounts of single-chip parallelism. The workshop will be conducted in an informal atmosphere, stressing interaction and discussion between presenters and audience.

Topics of interest include, but are not limited to

° hardware techniques (e.g. power saving, clocking, fault-tolerance)

° processor core architectures (homogeneous and heterogeneous)

° on-chip memory and cache (or cache-less) organization, and interconnects

° off-chip memory and I/O solutions, and multi-core coupling

° special purpose processors (accelerators)

° programming models (e.g. PRAM, BSP, Transactional Memory), languages, and software libraries

° implementation techniques (e.g. multi-threading, work-stealing)

° support and performance tools, performance evaluation

° parallel algorithms and applications

for/on highly parallel multi-core systems.

Authors are encouraged to submit original, unpublished research or overviews addressing issues in the design and application of highly parallel multi-core processors as outlined above.