COMMITTEE
Workshop on
Highly Parallel Processing on a Chip (HPPC)
August 28, 2007, IRISA, Rennes, France
in conjunction with
August 28-31, 2007, IRISA, Rennes, France.
WORKSHOP ORGANIZERS
Martti Forsell,
VTT, Finland
Jesper Larsson Träff, C&C Research labs, NEC Europe Ltd, Germany
PROGRAM COMMITTEE
Gianfranco Bilardi, University of Padova,
Italy
Taisuke Boku,
University of Tsukuba, Japan
Martti Forsell,
VTT, Finland
Jim Held, Intel,
USA
Peter Hofstee, IBM, USA
Ben Juurlink,
Technical University of Delft, The Netherlands
Darren
Kerbyson, Los Alamos National
Laboratory, USA
Lasse Natvig, NTNU,
Norway
Kunle Olukotun,
Stanford University, USA
Wolfgang Paul,
Saarland University, Germany
Andrea Pietracaprina,
University of Padova, Italy
Alex Ramirez,
Technical University of Catalonia and Barcelona Supercomputing
Center, Spain
Peter Sanders,
University of Karlsruhe, Germany
Thomas Sterling,
Caltech and Louisiana State University, USA
Jesper Larsson Träff, C&C Research labs, NEC Europe Ltd, Germany
Uzi Vishkin,
University of Maryland, USA
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Sponsors:
